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28F016SV 16-MBIT (1 MBIT x 16, 2 MBIT x 8) FlashFileTM MEMORY
Includes Commercial and Extended Temperature Specifications
SmartVoltage Technology User-Selectable 3.3V or 5V V CC User-Selectable 5V or 12V V PP 65 ns Access Time 1 Million Erase Cycles per Block 30.8 MB/sec Burst Write Transfer Rate 0.48 MB/sec Sustainable Write Transfer Rate Configurable x8 or x16 Operation 56-Lead TSOP and SSOP Type I Packages
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Backwards-Compatible with 28F016SA, 28F008SA Command Set Revolutionary Architecture Multiple Command Execution Program during Erase Command Super-Set of the Intel 28F008SA Page Buffer Program 2 A Typical Deep Power-Down 32 Independently Lockable Blocks State-of-the-Art 0.6 m ETOXTM IV Flash Technology
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Intel's 28F016SV 16-Mbit FlashFileTM memory is a revolutionary architecture which is the ideal choice for designing embedded direct-execute code and mass storage data/file flash memory systems. With innovative capabilities, low-power operation, user-selectable VPP voltage and high read/program performance, the 28F016SV enables the design of truly mobile, high-performance personal computing and communications products. The 28F016SV is the highest density, highest performance nonvolatile read/program solution for solid-state storage applications. Its symmetrically-blocked architecture (100% compatible with the 28F008SA 8-Mbit and 28F016SA 16-Mbit FlashFile memories), extended cycling, flexible VCC and VPP voltage (SmartVoltage technology), fast program and read performance and selective block locking, provide a highly-flexible memory component suitable for Resident Flash Arrays, high-density memory cards and PCMCIA-ATA flash drives. The 28F016SV's dual read voltage enables the design of memory cards which can be read/written in 3.3V and 5V systems interchangeably. Its x8/x16 architecture allows optimization of the memory-to-processor interface. The flexible block locking option enables bundling of executable application software in a Resident Flash Array or memory card. The 28F016SV is manufactured on Intel's 0.6 m ETOX IV process technology.
July 1997
Order Number: 290528-007
7/11/97 11:03 AM
29052807.DOC
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F016SV may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-879-4683 or visit Intel's Website at http:\\www.intel.com
COPYRIGHT (c) INTEL CORPORATION, 1997 *Third-party brands and names are the property of their respective owners. CG-041493
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28F016SV FlashFileTM MEMORY
CONTENTS
PAGE PAGE 5.0 ELECTRICAL SPECIFICATIONS..................25 5.1 Absolute Maximum Ratings ........................25 5.2 Capacitance ...............................................26 5.3 DC Characteristics (VCC = 3.3V 0.3V) .....29 5.4 DC Characteristics (VCC = 5V 0.5V) 5V 0.25V) ..................................................33 5.5 Timing Nomenclature .................................37 5.6 AC Characteristics--Read Only Operations38 5.7 Power-Up and Reset Timings.....................43 5.8 AC Characteristics for WE#--Controlled Command Write Operations .........................44 5.9 AC Characteristics for CE#--Controlled Command Write Operations ) ........................49 5.10 AC Characteristics for WE#--Controlled Page Buffer Program Operations..................54 5.11 AC Characteristics for CE#--Controlled Page Buffer Program Operations..................56 5.12 Erase and Word/Byte Program Performance.................................................58 6.0 MECHANICAL SPECIFICATIONS.................60 APPENDIX A: Device Nomenclature and Ordering Information .....................................61 APPENDIX B: Ordering Information .................63
1.0 INTRODUCTION .............................................7 1.1 Enhanced Features......................................7 1.2 Product Overview.........................................7 2.0 DEVICE PINOUT.............................................9 2.1 Lead Descriptions ......................................11 3.0 MEMORY MAPS ...........................................15 3.1 Extended Status Registers Memory Map ...16 4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS ................17 4.1 Bus Operations for Word-Wide Mode (BYTE# = VIH) ..............................................17 4.2 Bus Operations for Byte-Wide Mode (BYTE# = VIL)...............................................17 4.3 28F008SA--Compatible Mode Command Bus Definitions .............................................18 4.4 28F016SV--Performance Enhancement Command Bus Definitions ............................19 4.5 Compatible Status Register........................21 4.6 Global Status Register ...............................22 4.7 Block Status Register.................................23 4.8 Device Configuration Code.........................24
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28F016SV FlashFileTM MEMORY
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REVISION HISTORY
Description
Number -001 -002 Original Version
-003
Added 28F016SV-065/-070 at 5V VCC and 28F016SV-075 at 3.3V VCC. Improved burst write transfer rate to 30.8 MB/sec. Added 56-lead SSOP Type I packaging information. Changed VPPLK from 2V to 1.5V. Increased ICCR at 5V VCC and 3.3V VCC: ICCR1 from 30 mA (typ)/35 mA (max) to 40 mA (typ)/50 mA (max) @ V CC = 3.3V ICCR2 from 15 mA (typ)/20 mA (max) to 20 mA (typ)/30 mA (max) @ V CC = 3.3V ICCR1 from 50 mA (typ)/60 mA (max) to 75 mA (typ)/95 mA (max) @ V CC = 5V ICCR2 from 30 mA (typ)/35 mA (max) to 45 mA (typ)/55 mA (max) @ V CC = 5V Moved AC Characteristics for Extended Register Reads into separate table. Increased VPP MAX from 13V to 14V. Added Erase Suspend Command Latency times to Section 5.12 Modified Device Nomenclature Section to include SSOP package option and Ordering Information Changed definition of "NC." Removed "No internal connection to die" from description. Added "xx" to Upper Byte of Command (Data) Definition in Sections 4.3 and 4.4. Added Note to Sleep Command (Section 4.4) denoting that the chip must be de-selected in order for the power consumption in sleep mode to reach deep power-down levels. Modified parameters "V" and "I" of Section 5.1 to apply to "NC" pins. Increased IPPR (VPP Read Current) for VPP> VCC to 200 A at VCC = 3.3V and VCC = 5V Changed VCC = 5V DC Characteristics (Section 5.5) marked with Note 1 to indicate that these currents are specified for a CMOS rise/fall time (10% to 90%) of <5 ns and a TTL rise/fall time of <10 ns. Corrected the graphical representation of tWHGL and tEHGL in Figures 15 and 16. Increased Typical "Page Buffer Byte/Word Program Times" from 6.0 s to 8.0 s (Byte) and 12.1 s to 16.0 s (Word) @ VCC = 3.3V/5V and VPP = 5V: Increased Typ. "Byte/Word Program Times" (tWHRH1A/tWHRH1B) for VPP = 5V (Section 5.12) tWHRH1A from 16.5 s to 29.0 s and t WHRH1B from 24.0 s to 35.0 s at V CC =3.3V tWHRH1A from 11.0 s to 20.0 s and t WHRH1B from 16.0 s to 25.0 s at V CC = 5V Increased Typical "Block Program Times" (t WHRH2/tWHRH3)for VPP =5V (Section 5.12): t WHRH2 from 1.1 sec to 1.9 sec and t WHRH3 from 0.8 sec to 1.2 sec at V CC = 3.3V t WHRH2 from 0.8 sec to 1.4 sec and t WHRH3 from 0.6 sec to 0.85 sec at V CC = 5V Changed "Time from Erase Suspend Command to WSM Ready" spec name to "Erase Suspend Latency Time to Read;" modified typical values and added Min/Max values at VCC =3.3/5V and VPP =5V/12V (Section 5.12) Added "Erase Suspend Latency Time to Program" Specifications to Section 5.12 Minor cosmetic changes throughout document
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Number -004 Description -005
28F016SV FlashFileTM MEMORY
REVISION HISTORY (Continued)
Added 3/5# pin to Block Diagram (Figure 1), Pinout Configurations (Figures 2 and 3), Product Overview (Section 1.1) and Lead Descriptions (Section 2.1) Added 3/5# pin to Test Conditions of ICCS Specifications Added 3/5# pin (Y) to Timing Nomenclature (Section 5.5) Increased tPHQV Specifications at 5V VCC to 400 ns for E28F016SV 065 devices and 480 ns for E28F106SV 070 devices. Modified Power-Up and Reset Timings (Section 5.9) to include 3/5# pin: Removed t5VPH and t3VPH specifications; Added t PLYL, tPLYH, tYLPH, and tYHPH specifications Added tPHEL3 and tPHEL5 specifications to Power-Up and Reset Timings (Section 5.9) Corrected TSOP Mechanical Specification A 1 from 0.50 mm to 0.050 mm (Section 6.0) Corrected SSOP Mechanical Spec. B (max) from 0.20 mm to 0.40 mm (Section 6.0) Minor cosmetic changes throughout document. Updated DC Specifications: ICCD, IPPES Updated AC Specifications: Page Buffer Reads: (t AVAV, tAVQV, tELQV, and tFLQV/tFHQV) Page Buffer WE#-Controlled Command Writes (tELWL) CE#-Controlled Command Write Parameters (tAVAV, tELEH, tEHEL) Combined Commercial and Extended Temperature information into single datasheet. Updated AC Specifications: Page Buffer Reads: (t AVAV, tAVQV, tELQV, and tFLQV/tFHQV) Updated Disclaimer
-006 -007
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The implementation of a new architecture, with many enhanced features, will improve the device operating characteristics and result in greater product reliability and ease-of-use. The 28F016SV incorporates SmartVoltage technology, providing VCC operation at both 3.3V and 5V and program and erase capability at VPP = 12V or 5V. Operating at VCC = 3.3V, the 28F016SV consumes approximately one half the power consumption at 5V VCC, while 5V VCC provides the highest read performance capability. VPP = 5V operation eliminates the need for a separate 12V converter, while VPP = 12V maximizes program/erase performance. In addition to the flexible program and erase voltages, the dedicated VPP gives complete code protection with VPP VPPLK. A 3/5# input pin configures the device's internal circuitry for optimal 3.3V or 5V read/program operation. A Command User Interface (CUI) serves as the system interface between the microprocessor or microcontroller and the internal memory operation. Internal Algorithm Automation allows byte/word programs and block erase operations to be executed using a Two-Program command sequence to the CUI in the same way as the 28F008SA 8-Mbit FlashFileTM memory. A super-set of commands has been added to the basic 28F008SA command-set to achieve higher program performance and provide additional capabilities. These new commands and features include: * Page Buffer Programs to Flash * Command Queuing Capability * Automatic Data Programs during Erase * Software Locking of Memory Blocks * Two-Byte Systems Successive Programs in 8-bit
1.0 INTRODUCTION
The documentation of the Intel 28F016SV memory device includes this datasheet, a detailed user's manual, and a number of application notes and design tools, all of which are referenced in Appendix B. The datasheet is intended to give an overview of the chip feature-set and of the operating AC/DC specifications. The 16-Mbit Flash Product Family User's Manual provides complete descriptions of the user modes, system interface examples and detailed descriptions of all principles of operation. It also contains the full list of software algorithm flowcharts, and a brief section on compatibility with the Intel 28F008SA. A significant 28F016SV change occurred between datasheet revisions 290528-003 and 290528-004. This change centers around the addition of a 3/5# pin to the device's pinout configuration. Figures 2 and 3 show the 3/5# pin assignment for TSOP and SSOP Type 1 packages. Intel recommends that all customers obtain the latest revisions of 28F016SV documentation.
1.1 Enhanced Features
The 28F016SV is backwards compatible with the 28F016SA and offers the following enhancements: * SmartVoltage Technology Selectable 5V or 12V VPP * VPP Level Bit in Block Status Register * Additional RY/BY# Configuration Pulse-On-Program/Erase * Additional Upload Device Information Command Feedback Device Proliferation Code Device Configuration Code
1.2 Product Overview
The 28F016SV is a high-performance, 16-Mbit (16,777,216-bit) block erasable, nonvolatile random access memory, organized as either 1 Mword x 16 or 2 Mbyte x 8. The 28F016SV includes thirty-two 64-KB (65,536 byte) blocks or thirty-two 32-KW (32,768 word) blocks. A chip memory map is shown in Figure 4.
* Erase All Unlocked Blocks Writing of memory data is performed in either byte or word increments typically within 6 s (12V VPP)--a 33% improvement over the 28F008SA. A block erase operation erases one of the 32 blocks in typically 0.6 sec (12V VPP), independent of the other blocks, which is about a 65% improvement over the 28F008SA. 7
28F016SV FlashFileTM MEMORY
Each block can be written and erased a minimum of 100,000 cycles. Systems can achieve one million Block Erase Cycles by providing wearleveling algorithms and graceful block retirement. These techniques have already been employed in many flash file systems and hard disk drive designs. The 28F016SV incorporates two Page Buffers of 256 bytes (128 words) each to allow page data programs. This feature can improve a system program performance by up to 4.8 times over previous flash memory devices, which have no Page Buffers. All operations are started by a sequence of Program commands to the device. Three Status Registers (described in detail later in this datasheet) and a RY/BY# output pin provide information on the progress of the requested operation. While the 28F008SA requires an operation to complete before the next operation can be requested, the 28F016SV allows queuing of the next operation while the memory executes the current operation. This eliminates system overhead when writing several bytes in a row to the array or erasing several blocks at the same time. The 28F016SV can also perform program operations to one block of memory while performing erase of another block. The 28F016SV provides selectable block locking to protect code or data such as Device Drivers, PCMCIA card information, ROM-Executable O/S or Application Code. Each block has an associated nonvolatile lock-bit which determines the lock status of the block. In addition, the 28F016SV has a master Write Protect pin (WP#) which prevents any modifications to memory blocks whose lock-bits are set. The 28F016SV contains three types of Status Registers to accomplish various functions: * A Compatible Status Register (CSR) which is 100% compatible with the 28F008SA FlashFile memory Status Register. The CSR, when used alone, provides a straightforward upgrade capability to the 28F016SV from a 28F008SAbased design. * A Global Status Register (GSR) which informs the system of command Queue status, Page Buffer status, and overall Write State Machine (WSM) status. 8
* 32 Block Status Registers (BSRs) which provide block-specific status information such as the block lock-bit status. The GSR and BSR memory maps for byte-wide and word-wide modes are shown in Figures 5 and 6. The 28F016SV incorporates an open drain RY/BY# output pin. This feature allows the user to OR-tie many RY/BY# pins together in a multiple memory configuration such as a Resident Flash Array. Other configurations of the RY/BY# pin are enabled via special CUI commands and are described in detail in the 16-Mbit Flash Product Family User's Manual. The 28F016SV's enhanced Upload Device Information command provides access to additional information that the 28F016SA previously did not offer. This command uploads the Device Revision Number, Device Proliferation Code and Device Configuration Code to the page buffer. The Device Proliferation Code for the 28F016SV is 01H, and the Device Configuration Code identifies the current RY/BY# configuration. Section 4.4 documents the exact page buffer address locations for all uploaded information. A subsequent Page Buffer Swap and Page Buffer Read command sequence is necessary to read the correct device information. The 28F016SV also incorporates a dual chipenable function with two input pins, CE0# and CE1#. These pins have exactly the same functionality as the regular chip-enable pin, CE#, on the 28F008SA. For minimum chip designs, CE1# may be tied to ground and system logic may use CE0# as the chip enable input. The 28F016SV uses the logical combination of these two signals to enable or disable the entire chip. Both CE0# and CE1# must be active low to enable the device. If either one becomes inactive, the chip will be disabled. This feature, along with the open drain RY/BY# pin, allows the system designer to reduce the number of control pins used in a large array of 16-Mbit devices. The BYTE# pin allows either x8 or x16 read/programs to the 28F016SV. BYTE# at logic low selects 8-bit mode with address A0 selecting between the low byte and high byte. On the other hand, BYTE# at logic high enables 16-bit operation with address A1 becoming the lowest
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operation) is required from RP# switching high until outputs are again valid. In the Deep PowerDown state, the WSM is reset (any current operation will abort) and the CSR, GSR and BSR registers are cleared. A CMOS standby mode of operation is enabled when either CE0# or CE1# transitions high and RP# stays high with all input control pins at CMOS levels. In this mode, the device typically draws an ICC standby current of 70 A at 5V V CC. The 28F016SV will be available in 56-lead, 1.2 mm thick, 14 mm x 20 mm TSOP and 56-lead, 1.8 mm thick, 16 mm x 23.7 SSOP Type I packages. The form factor and pinout of these two packages allow for very high board layout densities.
order address and address A0 is not used (don't care). A device block diagram is shown in Figure 1. The 28F016SV is specified for a maximum access time of 65 ns (tACC) at 5V operation (4.75V to 5.25V) over the commercial temperature range (0C to +70C). A corresponding maximum access time of 75 ns at 3.3V (3.0V to 3.6V and 0C to +70C) is achieved for reduced power consumption applications. The 28F016SV incorporates an Automatic Power Saving (APS) feature, which substantially reduces the active current when the device is in static mode of operation (addresses not switching). In APS mode, the typical ICC current is 1 mA at 5V (3.0 mA at 3.3V). A deep power-down mode of operation is invoked when the RP# (called PWD# on the 28F008SA) pin transitions low. This mode brings the device power consumption to less than 2.0 A, typically, and provides additional program protection by acting as a device reset pin during power transitions. A reset time of 400 ns (5V VCC
2.0 DEVICE PINOUT
The 28F016SV 56-lead TSOP and 56-lead SSOP Type I pinout configurations are shown in Figures 2 and 3.
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DQ 0-7 Output Buffer Input Buffer Input Buffer 3/5#
I/O Logic
DQ
8-15
Output Buffer
BYTE#
Data Queue Registers
ID Register
Output Multiplexer
CSR
Page Buffers
CE0#
ESRs
OE#
CE1 #
CUI
0-20
A
Data Comparator Input Buffer Y Decoder
WE# WP# RP#
Y Gating/Sensing
64-Kbyte Block 0
64-Kbyte Block 1
64-Kbyte Block 30
X Decoder
64-Kbyte Block 31
WSM
Address Queue Registers
RY/BY# V PP 3/5# VCC
Program/Erase Voltage Switch
Address Counter
GND
0528_01
Figure 1. 28F016SV Block Diagram Architectural Evolution Includes SmartVoltage Technology, Page Buffers, Queue Registers and Extended Registers
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2.1 Lead Descriptions
Type INPUT Name and Function BYTE-SELECT ADDRESS: Selects between high and low byte when device is in x8 mode. This address is latched in x8 data programs. Not used in x16 mode (i.e., the A 0 input buffer is turned off when BYTE# is high). A1-A15 INPUT WORD-SELECT ADDRESSES: Select a word within one 64-Kbyte block. A6-15 selects 1 of 1024 rows, and A 1-5 selects 16 of 512 columns. These addresses are latched during data programs. A16-A20 INPUT BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These addresses are latched during data programs, erase and lock block operations. DQ0-DQ7 INPUT/OUTPUT LOW-BYTE DATA BUS: Inputs data and commands during CUI program cycles. Outputs array, buffer, identifier or status data in the appropriate read mode. Floated when the chip is de-selected or the outputs are disabled. DQ8-DQ15 INPUT/OUTPUT HIGH-BYTE DATA BUS: Inputs data during x16 data program operations. Outputs array, buffer or identifier data in the appropriate read mode; not used for Status Register reads. Floated when the chip is deselected or the outputs are disabled. CE0#, CE1# INPUT CHIP ENABLE INPUTS: Activate the device's control logic, input buffers, decoders and sense amplifiers. With either CE0# or CE1# high, the device is de-selected and power consumption reduces to standby levels upon completion of any current data program or erase operations. Both CE0# and CE1# must be low to select the device. All timing specifications are the same for both signals. Device Selection occurs with the latter falling edge of CE 0# or CE1#. The first rising edge of CE0# or CE1# disables the device. RP# INPUT RESET/POWER-DOWN: RP# low places the device in a deep powerdown state. All circuits that consume static power, even those circuits enabled in standby mode, are turned off. When returning from deep power-down, a recovery time of tPHQV is required to allow these circuits to power-up. When RP# goes low, any current or pending WSM operation(s) are terminated, and the device is reset. All Status Registers return to ready (with all status flags cleared). Exit from deep power-down places the device in read array mode. OE# INPUT OUTPUT ENABLE: Gates device data through the output buffers when low. The outputs float to tri-state off when OE# is high. NOTE: CEx# overrides OE#, and OE# overrides WE#. WE# INPUT WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue Registers and Address Queue Latches. WE# is active low, and latches both address and data (command or array) on its rising edge. Page Buffer addresses are latched on the falling edge of WE#.
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2.1 Lead Descriptions (Continued)
Symbol RY/BY# Type OPEN DRAIN OUTPUT Name and Function
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WP#
INPUT
BYTE#
INPUT
3/5#
INPUT
VPP
SUPPLY
VCC
SUPPLY
GND NC
SUPPLY
READY/BUSY: Indicates status of the internal WSM. When low, it indicates that the WSM is busy performing an operation. RY/BY# floating indicates that the WSM is ready for new operations (or WSM has completed all pending operations), or erase is suspended, or the device is in deep power-down mode. This output is always active (i.e., not floated to tri-state off when OE# or CE0#, CE1# are high), except if a RY/BY# Pin Disable command is issued. WRITE PROTECT: Erase blocks can be locked by writing a nonvolatile lock-bit for each block. When WP# is low, those locked blocks as reflected by the Block-Lock Status bits (BSR.6), are protected from inadvertent data programs or erases. When WP# is high, all blocks can be written or erased regardless of the state of the lock-bits. The WP# input buffer is disabled when RP# transitions low (deep power-down mode). BYTE ENABLE: BYTE# low places device in x8 mode. All data is then input or output on DQ0-7, and DQ8-15 float. Address A 0 selects between the high and low byte. BYTE# high places the device in x16 mode, and turns off the A0 input buffer. Address A1, then becomes the lowest order address. 3.3/5.0 VOLT SELECT: 3/5# high configures internal circuits for 3.3V operation. 3/5# low configures internal circuits for 5V operation. NOTE: Reading the array with 3/5# high in a 5V system could damage the device. Reference the power-up and reset timings (Section 5.7) for 3/5# switching delay to valid data. PROGRAM/ERASE POWER SUPPLY (12V 0.6V, 5V 0.5V) : For erasing memory array blocks or writing words/bytes/pages into the flash array. VPP = 5V 0.5V eliminates the need for a 12V converter, while connection to 12V 0.6V maximizes Program/Erase Performance. NOTE: Successful completion of program and erase attempts is inhibited with VPP at or below 1.5V. Program and erase attempts with VPP between 1.5V and 4.5V, between 5.5V and 11.4V, and above 12.6V produce spurious results and should not be attempted. DEVICE POWER SUPPLY (3.3V 0.3V, 5V 0.5V, 5.0 0.25V): To switch 3.3V to 5V (or vice versa), first ramp V CC down to GND, and then power to the new VCC voltage. Do not leave any power pins floating. GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins floating. NO CONNECT: Lead may be driven or left floating.
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28F016SV FlashFileTM MEMORY
28F016SA 28F032SA
3/5# CE1 # CE2 # A20 A19 A 18 A17 A16 V CC A 15 A 14 A 13 A 12 CE 0# V PP RP# A 11 A 10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1
3/5# CE 1 # NC A20 A19 A 18 A17 A16 V CC A 15 A 14 A 13 A 12 CE 0# V PP RP# A 11 A 10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1
3/5# CE1 # NC A20 A19 A 18 A17 A16 V CC A 15 A 14 A 13 A 12 CE 0# V PP RP# A 11 A 10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
E28F016SV 56-LEAD TSOP PINOUT
14 mm x 20 mm TOP VIEW
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
WP# WE# OE# RY/BY# DQ15 DQ 7 DQ 14 DQ 6 GND DQ 13 DQ5 DQ12 DQ4 VCC GND DQ11 DQ 3 DQ 10 DQ 2 VCC DQ 9 DQ 1 DQ 8 DQ 0 A0 BYTE# NC NC
WP# WE# OE# RY/BY# DQ15 DQ 7 DQ 14 DQ 6 GND DQ 13 DQ5 DQ12 DQ4 VCC GND DQ11 DQ 3 DQ 10 DQ 2 VCC DQ 9 DQ 1 DQ 8 DQ 0 A0 BYTE# NC NC
WP# WE# OE# RY/BY# DQ15 DQ7 DQ14 DQ6 GND DQ 13 DQ5 DQ12 DQ4 VCC GND DQ11 DQ 3 DQ 10 DQ 2 VCC DQ 9 DQ 1 DQ 8 DQ 0 A0 BYTE# NC NC
NOTE: 56-lead TSOP Mechanical Diagrams and dimensions are shown at the end of this datasheet.
0528_02
Figure 2. 28F016SV 56-Lead TSOP Pinout Configuration Shows Compatibility with 28F016SA/28F032SA
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56 55 54 53 52 51 50 49 48 47 46 DA28F016SV 56-LEAD SSOP STANDARD PINOUT 16 mm x 23.7 mm TOP VIEW 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VPP R/P# A11 A10 A9 A1 A2 A3 A4 A5 A6 A7 GND A8 VCC DQ 9 DQ 1 DQ 8 DQ 0 A0 BYTE# NC NC DQ2 DQ 10 DQ 3 DQ 11 GND 28F016SA VPP R/P# A11 A10 A9 A1 A2 A3 A4 A5 A6 A7 GND A8 VCC DQ 9 DQ 1 DQ 8 DQ 0 A0 BYTE# NC NC DQ2 DQ 10 DQ 3 DQ 11 GND
28F016SA CE0 # A 12 A 13 A 14 A 15 3/5# CE1 # NC A 20 A 19 A 18 A 17 A 16 VCC GND DQ 6 DQ 14 DQ 7 DQ 15 RY/BY# OE# WE# WP# DQ13 DQ5 DQ12 DQ4 VCC
CE0 # A12 A13 A14 A15 3/5# CE1 # NC A 20 A 19 A 18 A 17 A 16 VCC GND DQ 6 DQ 14 DQ 7 DQ 15 RY/BY# OE# WE# WP# DQ13 DQ5 DQ12 DQ4 VCC
1 2 3 4
5
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
NOTE: 56-lead SSOP Mechanical Diagrams and dimensions are shown at the end of this datasheet.
0528_03
Figure 3. 56-Lead SSOP Pinout Configuration
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3.0 MEMORY MAPS
A[20-0]
1FFFFF 1F0000 1EFFFF 1E0000 1DFFFF 1D0000 1CFFFF 1C0000 1BFFFF 1B0000 1AFFFF 1A0000 19FFFF 190000 18FFFF 180000 17FFFF 170000 16FFFF 160000 15FFFF 150000 14FFFF 140000 13FFFF 130000 12FFFF 120000 11FFFF 110000 10FFFF 100000 0FFFFF 0F0000 0EFFFF 0E0000 0DFFFF 0D0000 0CFFFF 0C0000 0BFFFF 0B0000 0AFFFF 0A0000 09FFFF 090000 08FFFF 080000 07FFFF 070000 06FFFF 060000 05FFFF 050000 04FFFF 040000 03FFFF 030000 02FFFF 020000 01FFFF 010000 00FFFF 000000
A[20-1] 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FFFFF F8000 F7FFF F0000 EFFFF E8000 E7FFF E0000 DFFFF D8000 D7FFF D0000 CFFFF C8000 C7FFF C0000 BFFFF B8000 B7FFF B0000 A8FFF A8000 A7FFF A0000 9FFFF 98000 97FFF 90000 8FFFF 88000 87FFF 80000 7FFFF 78000 77FFF 70000 6FFFF 68000 67FFF 60000 5FFFF 58000 57FFF 50000 4FFFF 48000 47FFF 40000 3FFFF 38000 37FFF 30000 2FFFF 28000 27FFF 20000 1FFFF 18000 17FFF 10000 0FFFF 08000 07FFF 00000
32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Byte-Wide (x8) Mode
Word-Wide (x16) Mode
0528_04
Figure 4. 28F016SV Memory Maps (Byte-Wide and Word-Wide Modes) 15
28F016SV FlashFileTM MEMORY
3.1 Extended Status Registers Memory Map
E
x16 MODE RESERVED A[20-1] F8003H GSR RESERVED F8002H BSR 31 F8001H RESERVED RESERVED
x8 MODE RESERVED GSR RESERVED BSR 31 RESERVED RESERVED
A[20-0] 1F0006H 1F0005H 1F0004H 1F0003H 1F0002H 1F0001H
. . .
1F0000H
. . .
F8000H
010002H
08001H
RESERVED
RESERVED
000006H RESERVED 000005H GSR 000004H RESERVED 000003H BSR 0 RESERVED RESERVED
000002H
00003H RESERVED GSR 00002H
RESERVED
BSR 0
000001H 000000H
0528_05
RESERVED
RESERVED
00001H
00000H
0528_06
Figure 5. Extended Status Register Memory Map (Byte-Wide Mode)
Figure 6. Extended Status Register Memory Map (Word-Wide Mode)
16
E
Read Standby Device ID Write
28F016SV FlashFileTM MEMORY
4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS 4.1 Bus Operations for Word-Wide Mode (BYTE# = VIH)
Mode Notes 1,2,7 1,6,7 1,6,7 RP# VIH VIH VIH CE1# VIL VIL VIL VIH VIH X VIL VIL VIL CE0# VIL VIL VIH VIL VIH X VIL VIL VIL OE# VIL VIH X WE# VIH VIH X A1 X X X DQ0-15 DOUT High Z High Z RY/BY# X X X
Output Disable
Deep Power-Down Manufacturer ID
1,3 4 4,8 1,5,6
VIL VIH VIH VIH
X VIL VIL VIH
X VIH VIH VIL
X VIL VIH X
High Z 0089H 66A0H DIN
VOH VOH VOH X
4.2 Bus Operations for Byte-Wide Mode (BYTE# = VIL)
Mode Read Output Disable Standby Notes 1,2,7 1,6,7 1,6,7 RP# VIH VIH VIH CE1# VIL VIL VIL VIH VIH X VIL VIL VIL CE0# VIL VIL VIH VIL VIH X VIL VIL VIL OE# VIL VIH X WE# VIH VIH X A0 X X X DQ0-7 DOUT High Z High Z RY/BY# X X X
Deep Power-Down Manufacturer ID Device ID Write
1,3 4 4,8 1,5,6
VIL VIH VIH VIH
X VIL VIL VIH
X VIH VIH VIL
X VIL VIH X
High Z 89H A0H DIN
VOH VOH VOH X
NOTES: 1. X can be VIH or VIL for address or control pins except for RY/BY#, which is either VOL or VOH. 2. RY/BY# output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode. RY/BY# will be at VOH if it is tied to VCC through a resistor. RY/BY# at VOH is independent of OE# while a WSM operation is in progress. 3. RP# at GND 0.2V ensures the lowest deep power-down current. 4. A0 and A1 at VIL provide device manufacturer codes in x8 and x16 modes respectively. A0 and A1 at VIH provide device ID codes in x8 and x16 modes respectively. All other addresses are set to zero. 5. Commands for erase, data program, or lock-block operations can only be completed successfully when V = VPPH1 or PP VPP = VPPH2. 6. While the WSM is running, RY/BY# in level-mode (default) stays at VOL until all operations are complete. RY/BY# goes to VOH when the WSM is not busy or in erase suspend mode. 7. RY/BY# may be at VOL while the WSM is busy performing various operations (for example, a Status Register read during a program operation). 8. The 28F016SV shares an identical device identifier (66A0H in word-wide mode, A0H in byte-wide mode) with the 28F016SA. See application note AP-393 28F016SV Compatibility with 28F016SA for software and hardware techniques to differentiate between the 28F016SV and 28F016SA.
17
28F016SV FlashFileTM MEMORY
4.3 28F008SA--Compatible Mode Command Bus Definitions
First Bus Cycle Command Read Array Intelligent Identifier Read Compatible Status Register Clear Status Register Word/Byte Program Alternate Word/Byte Program Block Erase/Confirm Erase Suspend/Resume
ADDRESS AA = Array Address BA = Block Address IA = Identifier Address PA = Program Address X = Don't Care
E
Second Bus Cycle Oper Addr AA IA X Data(4) AD ID CSRD Write Write Write Write PA PA BA X PD PD xxD0H xxD0H
Notes
Oper Write
Addr X X X X X X X X
Data(4)
xxFFH xx90H xx70H xx50H xx40H xx10H xx20H xxB0H
Read Read Read
1 2 3
Write Write Write Write Write Write Write
DATA AD = Array Data CSRD = CSR Data ID = Identifier Data PD = Program Data
NOTES: 1. Following the Intelligent Identifier command, two Read operations access the manufacturer and device signature codes. 2. The CSR is automatically available after device enters data program, erase, or suspend operations. 3. Clears CSR.3, CSR.4 and CSR.5. Also clears GSR.5 and all BSR.5, BSR.4 and BSR.2 bits. See Status Register definitions. 4. The upper byte of the data bus (DQ8-15) during command writes is a "Don't Care" in x16 operation of the device.
18
E
Read Extended Status Register
28F016SV FlashFileTM MEMORY
4.4 28F016SV--Performance Enhancement Command Bus Definitions
Command Mode Notes First Bus Cycle Oper 1 Write Addr X Data
(13)
Second Bus Cycle Oper Read Addr RA Data
(13)
Third Bus Cycle Oper Addr Data
xx71H
GSRD BSRD
Page Buffer Swap Read Page Buffer Single Load to Page Buffer Sequential Load to Page Buffer x8 x16 Page Buffer Write to Flash x8 x16 Two-Byte Program Lock Block/Confirm Upload Status Bits/Confirm Upload Device Information/Confirm Erase All Unlocked Blocks/Confirm RY/BY# Enable to Level-Mode RY/BY# Pulse-On-Write RY/BY# Pulse-On-Erase RY/BY# Disable RY/BY# Pulse-OnWrite/Erase Sleep Abort ADDRESS BA = Block Address PBA = Page Buffer Address RA = Extended Register Address PA = Program Address X = Don't Care x8
7
Write Write Write
X X X
xx72H xx75H xx74H Read Write PBA PBA PD PD
4,6,10 4,5,6,10 3,4,9,10 4,5,10 3
Write Write Write Write Write Write
X X X X X X X
xxE0H xxE0H xx0CH xx0CH xxFBH xx77H xx97H
Write Write Write Write Write Write Write
X X A0 X A0 BA X
BCL WCL BC(L,H) WCL WD(L,H) xxD0H xxD0H
Write Write Write Write Write
X X PA PA PA
BCH WCH BC(H,L) WCH WD(H,L)
2
Write
11
Write
X
xx99H
Write
X
xxD0H
Write
X
xxA7H
Write
X
xxD0H
8
Write
X
xx96H
Write
X
xx01H
8
Write
X
xx96H
Write
X
xx02H
8
Write
X
xx96H
Write
X
xx03H
8 8
Write Write
X X
xx96H xx96H
Write Write
X X
xx04H xx05H
12
Write Write
X X
xxF0H xx80H
DATA AD = Array Data PD = Page Buffer Data BSRD = BSR Data GSRD = GSR Data
WC (L,H) = Word Count (Low, High) BC (L,H) = Byte Count (Low, High) WD (L,H) = Write Data (Low, High)
19
28F016SV FlashFileTM MEMORY
NOTES: 1. RA can be the GSR address or any BSR address. See Figures 4 and 5 for Extended Status Register memory maps. 2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the actual lock-bit status. 3. A0 is automatically complemented to load second byte of data. BYTE# must be at VIL. A0 value determines which WD/BC is supplied first: A0 = 0 looks at the WDL/BCL, A0 = 1 looks at the WDH/BCH. 4. BCH/WCH must be at 00H for this product because of the 256-byte (128-word) Page Buffer size, and to avoid writing the Page Buffer contents to more than one 256-byte segment within an array block. They are simply shown for future Page Buffer expandability. 5. In x16 mode, only the lower byte DQ0-7 is used for WCL and WCH. The upper byte DQ8-15 is a don't care. 6. PBA and PD (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle, which is not shown. 7. This command allows the user to swap between available Page Buffers (0 or 1). 8. These commands reconfigure RY/BY# output to one of three pulse-modes or enable and disable the RY/BY# function. 9. Program address, PA, is the Destination address in the flash array which must match the Source address in the Page Buffer. Refer to the 16-Mbit Flash Product Family User's Manual. 10. BCL = 00H corresponds to a byte count of 1. Similarly, WCL = 00H corresponds to a word count of 1. 11. After writing the Upload Device Information command and the Confirm command, the following information is output at Page Buffer addresses specified below: Address 06H, 07H (Byte Mode) 03H (Word Mode) 1EH (Byte Mode) 0FH (DQ0-7)(Word Mode) 1FH (Byte Mode) 0FH (DQ8-15)(Word Mode) Information Device Revision Number Device Revision Number Device Configuration Code Device Configuration Code Device Proliferation Code (01H) Device Proliferation Code (01H)
E
A page buffer swap followed by a page buffer read sequence is necessary to access this information. The contents of all other Page Buffer locations, after the Upload Device Information command is written, are reserved for future implementation by Intel Corporation. See Section 4.8 for a description of the Device Configuration Code. This code also corresponds to data written to the 28F016SV after writing the RY/BY# Reconfiguration command. 12. To ensure that the 28F016SV's power consumption during sleep mode reaches the deep power-down current level, the system also needs to de-select the chip by taking either or both CE0# or CE1# high. 13. The upper byte of the data bus (DQ8-15) during command writes is a "Don't Care" in x16 operation of the device.
20
E
4.5
WSMS 7
28F016SV FlashFileTM MEMORY
Compatible Status Register
ESS 6 ES 5 DWS 4 VPPS 3 R 2 NOTES: R 1 R 0
CSR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy
RY/BY# output or WSMS bit must be checked to determine completion of an operation (erase, erase suspend, or data program) before the appropriate Status bit (ESS, ES or DWS) is checked for success.
CSR.6 = ERASE-SUSPEND STATUS 1 = Erase Suspended 0 = Erase in Progress/Completed CSR.5 = ERASE STATUS 1 = Error in Block Erasure 0 = Successful Block Erase CSR.4 = DATA-WRITE STATUS 1 = Error in Data Program 0 = Data Program Successful CSR.3 = VPP STATUS 1 = VPP Error Detect, Operation Abort 0 = VPP OK The VPPS bit, unlike an A/D converter, does not provide continuous indication of VPP level. The WSM interrogates VPP's level only after the Data Program or Erase command sequences have been entered, and informs the system if V PP has not been switched on. VPPS is not guaranteed to report accurate feedback between VPPLK(max) and VPPH1(min), between VPPH1(max) and VPPH2(min) and above VPPH2(max). If DWS and ES are set to "1" during an erase attempt, an improper command sequence was entered. Clear the CSR and attempt the operation again.
CSR.2-0 = RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use; mask them out when polling the CSR.
21
28F016SV FlashFileTM MEMORY
4.6 Global Status Register
WSMS 7 OSS 6 DOS 5 DSS 4 QS 3 NOTES: GSR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy
[1]
E
PBAS 2 PBS 1 PBSS 0 RY/BY# output or WSMS bit must be checked to determine completion of an operation (block lock, suspend, any RY/BY# reconfiguration, Upload Status Bits, erase or data program) before the appropriate Status bit (OSS or DOS) is checked for success.
GSR.6 = OPERATION SUSPEND STATUS 1 = Operation Suspended 0 = Operation in Progress/Completed GSR.5 = DEVICE OPERATION STATUS 1 = Operation Unsuccessful 0 = Operation Successful or Currently Running GSR.4 = DEVICE SLEEP STATUS 1 = Device in Sleep 0 = Device Not in Sleep MATRIX 5/4 0 0 = Operation Successful or Currently Running 0 1 = Device in Sleep Mode or Pending Sleep 1 0 = Operation Unsuccessful 1 1 = Operation Unsuccessful or Aborted GSR.3 = QUEUE STATUS 1 = Queue Full 0 = Queue Available GSR.2 = PAGE BUFFER AVAILABLE STATUS 1 = One or Two Page Buffers Available 0 = No Page Buffer Available GSR.1 = PAGE BUFFER STATUS 1 = Selected Page Buffer Ready 0 = Selected Page Buffer Busy GSR.0 = PAGE BUFFER SELECT STATUS 1 = Page Buffer 1 Selected 0 = Page Buffer 0 Selected
NOTE: 1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block. GSR.7 provides indication when all queued operations are completed.
If operation currently running, then GSR.7 = 0. If device pending sleep, then GSR.7 = 0.
Operation aborted: Unsuccessful due to Abort command.
The device contains two Page Buffers.
Selected Page Buffer is currently busy with WSM operation
22
E
BS 7
28F016SV FlashFileTM MEMORY
4.7 Block Status Register
BLS 6 BOS 5 BOAS 4 QS 3 VPPS 2 VPPL 1 R 0
BSR.7 = BLOCK STATUS 1 = Ready 0 = Busy
NOTES: [1] RY/BY# output or BS bit must be checked to determine completion of an operation (block lock, suspend, erase or data program) before the appropriate Status bits (BOS, BLS) is checked for success.
BSR.6 = BLOCK LOCK STATUS 1 = Block Unlocked for Program/Erase 0 = Block Locked for Program/Erase BSR.5 = BLOCK OPERATION STATUS 1 = Operation Unsuccessful 0 = Operation Successful or Currently Running BSR.4 = BLOCK OPERATION ABORT STATUS 1 = Operation Aborted 0 = Operation Not Aborted MATRIX 5/4 0 0 = Operation Successful or Currently Running 0 1 = Not a Valid Combination 1 0 = Operation Unsuccessful 1 1 = Operation Aborted BSR.3 = QUEUE STATUS 1 = Queue Full 0 = Queue Available BSR.2 = VPP STATUS 1 = VPP Error Detect, Operation Abort 0 = VPP OK BSR.1 = VPP LEVEL 1 = VPP Detected at 5V 10% 0 = VPP Detected at 12V 5% BSR.1 is not guaranteed to report accurate feedback between the VPPH1 and VPPH2 voltage ranges. Programs and erases with VPP between VPPLK(max) and VPPH1(min), between VPPH1(max) and VPPH2(min), and above VPPH2(max) produce spurious results and should not be attempted. BSR.1 was a RESERVED bit on the 28F016SA. The BOAS bit will not be set until BSR.7 = 1.
Operation halted via Abort command.
BSR.0 = RESERVED FOR FUTURE ENHANCEMENTS This bits is reserved for future use; mask it out when polling the BSRs.
NOTE: 1. When multiple operations are queued, checking BSR.7 only provides indication of completion or that particular block. GSR.7 provides indication when all queued operations are completed.
23
28F016SV FlashFileTM MEMORY
4.8 Device Configuration Code
R 7 R 6 R 5 R 4 R 3 RB2 2 RB1 1
E
RB0 0 NOTES: Undocumented combinations of RB2-RB0 are reserved by Intel Corporation for future implementations and should not be used.
DCC.2-DCC.0 = RY/BY# CONFIGURATION (RB2-RB0) 001 = Level Mode (Default) 010 = Pulse-On-Program 011 = Pulse-On-Erase 100 = RY/BY# Disabled 101 = Pulse-On-Program/Erase
DCC.7-DCC.3 = RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use; mask them out when reading the Device Configuration Code. Set these bits to "0" when writing the desired RY/BY# configuration to the device.
24
E
5.0 ELECTRICAL SPECIFICATIONS 5.1 Absolute Maximum Ratings*
Temperature Under Bias ....................0C to +80C Storage Temperature ...................-65C to +125C VCC = 3.3V 0.3V Systems Sym TA VCC VPP V I IOUT Parameter Operating Temperature, Commercial VCC with Respect to GND VPP Supply Voltage with Respect to GND Voltage on Any Pin (except V CC,VPP) with Respect to GND Current into Any Non-Supply Pin Output Short Circuit Current Notes 1 2 2,3 2,5 5 4 Min 0 -0.2 -0.2 -0.5
28F016SV FlashFileTM MEMORY
NOTICE: This is a production datasheet. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. *WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
Max 70 7.0 14.0 VCC + 0.5 30 100
Units C V V V mA mA
Test Conditions Ambient Temperature
VCC = 5V 0.5V, 5V 0.25V Systems (6) Sym TA VCC VPP V I IOUT Parameter Operating Temperature, Commercial VCC with Respect to GND VPP Supply Voltage with Respect to GND Voltage on Any Pin (except V CC,VPP) with Respect to GND Current into Any Non-Supply Pin Output Short Circuit Current Notes 1 2 2,3 2,5 5 4 Min 0 -0.2 -0.2 -2.0 Max 70 7.0 14.0 7.0 30 100 Units C V V V mA mA Test Conditions Ambient Temperature
NOTES: 1. Operating temperature is for commercial product defined by this specification. 2. Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20 ns. Maximum DC voltage on input/output pins is VCC + 0.5V which, during transitions, may overshoot to VCC + 2.0V for periods <20 ns. 3. Maximum DC voltage on VPP may overshoot to +14.0V for periods <20 ns. 4. Output shorted for no more than one second. No more than one output shorted at a time. 5. This specification also applies to pins marked "NC." 6. 5% VCC specifications refer to the 28F016SV-065 and 28F016SV-070 in its high speed test configuration.
25
28F016SV FlashFileTM MEMORY
5.2 Capacitance
For a 3.3V 0.3V System: Sym CIN COUT CLOAD Parameter Capacitance Looking into an Address/Control Pin Capacitance Looking into an Output Pin Load Capacitance Driven by Outputs for Timing Specifications Notes 1 1 1,2 Typ 6 8 Max 8 12 50 Units pF pF pF
E
Test Conditions TA = +25C, f = 1.0 MHz TA = +25C, f = 1.0 MHz Notes 1 1 1,2 Typ 6 8 Max 8 12 100 30 Units pF pF pF pF Test Conditions TA = +25C, f = 1.0 MHz TA = +25C, f = 1.0 MHz For VCC = 5V 0.5V For VCC = 5V 0.25V
For 5V 0.5V, 5V 0.25V System: Sym CIN COUT CLOAD Parameter Capacitance Looking into an Address/Control Pin Capacitance Looking into an Output Pin Load Capacitance Driven by Outputs for Timing Specifications
NOTE: 1. Sampled, not 100% tested. Guaranteed by design. 2. To obtain iBIS models for the 28F016SV, please contact your local Intel/Distribution Sales Office.
26
E
2.4 INPUT 0.45 0.8 2.0 TEST POINTS
3.0 INPUT 0.0 1.5 TEST POINTS
28F016SV FlashFileTM MEMORY
2.0 OUTPUT 0.8
AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0." Input timing begins at VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.
0528_07
Figure 7. Transient Input/Output Reference Waveform for VCC = 5V 10% (Standard Testing Configuration)(1)
1.5
OUTPUT
AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.5V. Input rise and fall times (10% to 90%) <10 ns.
0528_08
Figure 8. Transient Input/Output Reference Waveform for VCC = 3.3V 0.3V and VCC = 5V 5% (High Speed Testing Configuration)(2)
NOTES:
1. Testing characteristics for 28F016SV-070 (Standard Testing Configuration) and 28F016SV-080. 2. Testing characteristics for 28F016SV-065/28F016SV-075 and 28F016SV-70 (High Speed Testing Configuration)/ 28F016SV-120.
27
28F016SV FlashFileTM MEMORY
E
Test Point
2.5 ns of 25 Transmission Line
From Output under Test
Total Capacitance = 100 pF
0528_09
Figure 9. Transient Equivalent Testing Load Circuit (28F016SV-070/-080 at VCC = 5V 10%)
2.5 ns of 50 Transmission Line
From Output under Test
Test Point
Total Capacitance = 50 pF
0528_10
Figure 10. Transient Equivalent Testing Load Circuit (28F016SV-075/-120 at VCC = 3.3V 0.3V)
2.5 ns of 83 Transmission Line
From Output under Test
Test Point
Total Capacitance = 30 pF
0528_11
Figure 11. High Speed Transient Equivalent Testing Load Circuit (28F016SV-065/-070 at VCC = 5V 5%)
28
E
Sym ILI ILO ICCS
28F016SV FlashFileTM MEMORY
5.3 DC Characteristics
VCC = 3.3V 10%V, T A = 0C to +70C, -40C to +70C 3/5# = Pin Set High for 3.3V Operations Temp Parameter Input Load Current Output Leakage Current VCC Standby Current Notes 1 1 Commercial Min Typ Max 1 10 Min Extended Typ Max 1 10 Units A A Test Conditions VCC = VCC Max VIN = VCC or GND VCC = VCC Max VOUT = VCC or GND VCC = VCC Max CE0#, CE1#, RP# = VCC 0.2V BYTE#, WP#, 3/5# = VCC 0.2V or GND 0.2V VCC = VCC Max CE0#, CE1#, RP# = VIH BYTE#, WP#, 3/5# = VIH or VIL RP# = GND 0.2V BYTE# = VCC 0.2V or GND 0.2V VCC = VCC Max CMOS: CE0#, CE1# = GND 0.2V, BYTE# = GND 0.2V or VCC 0.2V, Inputs = GND 0.2V or VCC 0.2V TTL: CE0#, CE1# = VIL, BYTE# = V IL or VIH, Inputs = VIL or VIH f = 8 MHz, I OUT = 0 mA
1,5
70
130
70
130
A
1
4
1
4
mA
ICCD
VCC Deep Power-Down Current VCC Read Current
1
2
10
5
15
A
ICCR1
1,4,5
40
50
40
55
mA
29
28F016SV FlashFileTM MEMORY
5.3 DC Characteristics (Continued)
VCC = 3.3V 10%V, T A = 0C to +70C, -40C to +70C 3/5# = Pin Set High for 3.3V Operations Temp Sym ICCR2 Parameter VCC Read Current Notes 1,4, 5,6 Commercial Min Typ 20 Max 30 Min Extended Typ 20 Max 35 Units mA
E
Test Conditions VCC = VCC Max CMOS: CE0#, CE1# = GND 0.2V, BYTE# = GND 0.2V or VCC 0.2V, Inputs = GND 0.2V or VCC 0.2V TTL: CE0#, CE1# = VIL, BYTE# = V IL or VIH, Inputs = VIL or VIH f = 4 MHz, I OUT = 0 mA VPP = 12V 5% Program in Progress VPP = 5V 10% Program in Progress VPP = 12V 5% Block Erase in Progress VPP = 5V 10% Block Erase in Progress CE0#, CE1# = VIH Block Erase Suspended VPP VCC VPP > VCC RP# = GND 0.2V
ICCW
VCC Program Current for Word or Byte
1,6
8
12
8
12
mA
8
17
8
17
mA
ICCE
VCC Block Erase Current
1,6
6
12
6
12
mA
9
17
9
17
mA
ICCES
IPPS IPPR IPPD
VCC Erase Suspend Current VPP Standby/ Read Current VPP Deep Power-Down Current
1,2
1
4
1
4
mA
1 1
1 30 0.2
10 200 5
3 70 0.2
10 200 5
A A A
30
E
Sym IPPW IPPE
28F016SV FlashFileTM MEMORY
5.3 DC Characteristics (Continued)
VCC = 3.3V 10%V, T A = 0C to +70C, -40C to +70C 3/5# = Pin Set High for 3.3V Operations Temp Parameter VPP Program Current for Word or Byte Notes 1,6 Commercial Min Typ 10 Max 15 Min Extended Typ 10 Max 15 Units mA Test Conditions VPP = 12V 5% Program in Progress VPP = 5V 10% Program in Progress VPP = 12V 5% Block Erase in Progress VPP = 5V 10% Block Erase in Progress VPP = VPPH1 or VPPH2 Block Erase Suspended
15
25
15
25
mA
VPP Erase Current
1,6
4
10
4
10
mA
14
20
14
20
mA
IPPES
VPP Erase Suspend Current Input Low Voltage Input High Voltage Output Low Voltage
1
30
200
70
200
A
VIL VIH VOL
6 6 6
-0.3 2.0
0.8 VCC + 0.3 0.4
0.8 VCC + 0.3 0.4
V V V VCC = VCC Min and IOL = 4 mA
31
28F016SV FlashFileTM MEMORY
5.3 DC Characteristics (Continued) VCC = 3.3V 0.3V, T A = 0C to +70C, -40C to +85C 3/5# = Pin Set High for 3.3V Operations Temp Comm/Ext
Sym VOH1 VOH2 VPPLK VPPH1 VPP Program/Erase Lock Voltage VPP during Program/Erase Operations VPP during Program/Erase Operations VCC Program/Erase Lock Voltage Parameter Output High Voltage Notes 6 6 3,6 3 Min 2.4 VCC- 0.2 0.0 4.5 5.0 1.5 5.5 Typ Max Units V V V V VCC = VCC Min IOH = -2.0 mA VCC = VCC Min IOH = -100 A
E
Test Conditions V
VPPH2
3
11.4
12.0
12.6
VLKO
NOTES:
2.0
V
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 3.3V, VPP = 12V or 5V, T = +25C. These currents are valid for all product versions (package and speeds). 2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of ICCES and ICCR. 3. Block erases, word/byte programs and lock block operations are inhibited when VPP VPPLK and not guaranteed in the ranges between VPPLK(max) and VPPH1(min), between VPPH1 (max) and VPPH2(min) and above VPPH2(max). 4. Automatic Power Savings (APS) reduces ICCR to 3.0 mA typical in static operation. 5. CMOS Inputs are either VCC 0.2V or GND 0.2V. TTL Inputs are either VIL or VIH. 6. Sampled, but not 100% tested. Guaranteed by design.
32
E
Sym ILI ILO ICCS
28F016SV FlashFileTM MEMORY
5.4 DC Characteristics
VCC = 5V 0.5V, 5V 0.25V, T A = 0C to +70C, -40C to +85C 3/5# = Pin Set Low for 5V Operations Temp Parameter Input Load Current Output Leakage Current VCC Standby Current Notes 1 1 Commercial Min Typ Max 1 10 Min Extended Typ Max 1 10 Units A A Test Conditions VCC = VCC Max VIN = VCC or GND VCC = VCC Max VOUT = VCC or GND VCC = VCC Max CE0#, CE1#, RP# = VCC 0.2V BYTE#, WP#, 3/5# = VCC 0.2V or GND 0.2V VCC = VCC Max, CE0#, CE1#, RP# = VIH BYTE#, WP#, 3/5# = VIH or VIL ICCD VCC Deep Power-Down Current VCC Read Current 1 2 10 5 15 A RP# = GND 0.2V BYTE# = VCC 0.2V or GND 0.2V VCC = VCC Max CMOS: CE0#, CE1# = GND 0.2V, BYTE# = GND 0.2V or VCC 0.2V, Inputs = GND 0.2V or, VCC 0.2V TTL: CE0#, CE1# = VIL, BYTE# = V IL or VIH, Inputs = VIL or VIH f = 10 MHz, I OUT = 0 mA
1,5
70
130
70
130
A
2
4
2
4
mA
ICCR1
1,4,5
75
95
75
105
mA
33
28F016SV FlashFileTM MEMORY
5.4 DC Characteristics (Continued)
VCC = 5V 0.5V, 5V 0.25V, T A = 0C to +70C, -40C to +85C 3/5# = Pin Set Low for 5V Operations Temp Sym ICCR2 Parameter VCC Read Current Notes 1,4, 5,6 Commercial Min Typ 45 Max 55 Min Extended Typ 45 Max 60 Units mA
E
Test Conditions VCC = VCC Max CMOS: CE0#, CE1# = GND 0.2V, BYTE# = GND 0.2V or VCC 0.2V, Inputs = GND 0.2V or VCC 0.2V TTL: CE0#, CE1# = VIL, BYTE# = V IL or VIH, Inputs = VIL or VIH f = 5 MHz, I OUT = 0 mA VPP = 12V 5% Program in Progress 25 40 25 40 mA VPP = 5V 10% Program in Progress
ICCW
VCC Program Current for Word or Byte
1,6
25
35
25
35
mA
ICCE
VCC Block Erase Current
1,6
18
25
18
25
mA
VPP = 12V 5% Block Erase in Progress
20
30
20
30
mA
VPP = 5V 10% Block Erase in Progress
ICCES
IPPS IPPR IPPD
VCC Erase Suspend Current VPP Standby /Read Current VPP Deep PowerDown Current
1,2
2
4
2
4
mA
1
1 30
10 200 5
3 70 0.2
10 200 5
A A A
CE0#, CE1# = VIH Block Erase Suspended VPP VCC VPP > VCC RP# = GND 0.2V
1
0.2
34
E
Sym IPPW IPPE
28F016SV FlashFileTM MEMORY
5.4 DC Characteristics (Continued)
VCC = 5V 0.5V, 5V 0.25V, T A = 0C to +70C, -40C to +85C 3/5# = Pin Set Low for 5V Operations Temp Parameter VPP Program Current for Word or Byte Notes 1,6 Commercial Min Typ 7 Max 12 Min Extended Typ 7 Max 12 Units mA Test Conditions VPP = 12V 5% Program in Progress VPP = 5V 10% Program in Progress VPP = 12V 5% Block Erase in Progress VPP = 5V 10% Block Erase in Progress VPP = VPPH1 or VPPH2 Block Erase Suspended
17
22
17
22
mA
VPP Block Erase Current
1,6
5
10
5
10
mA
16
20
16
20
mA
IPPES
VPP Erase Suspend Current Input Low Voltage Input High Voltage
1
30
200
30
200
A
VIL VIH
6 6
-0.5 2.0
0.8 VCC+ 0.5
0.8 VCC+ 0.5
V V
35
28F016SV FlashFileTM MEMORY
5.4 DC Characteristics (Continued)
VCC = 5V 0.5V, 5V 0.25V, TA = 0C to +70C, -40C to +85C 3/5# = Pin Set Low for 5V Operations Temp Comm/Extended Sym VOL VOH1 VOH2 VPPLK VPPH1 VPP Program/Erase Lock Voltage VPP during Program/Erase Operations VPP during Program/Erase Operations VCC Program/Erase Lock Voltage Parameter Output Low Voltage Output High Voltage Notes 6 6 6 3,6 0.85 VCC VCC - 0.4 0.0 4.5 5.0 1.5 5.5 V V Min Typ Max 0.45 Units V V
E
Test Conditions VCC = VCC Min IOL = 5.8 mA VCC = VCC Min IOH = -2.5 mA VCC = VCC Min IOH = -100 A
VPPH2
11.4
12.0
12.6
V
VLKO
2.0
V
NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5V, VPP = 12V or 5V, T = 25C. These currents are valid for all product versions (package and speeds) and are specified for a CMOS rise/fall time (10% to 90%) of <5 ns and a TTL rise/fall time of <10 ns. 2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of ICCES and ICCR. 3. Block erases, word/byte programs and lock block operations are inhibited when VPP VPPLK and not guaranteed in the ranges between VPPLK(max) and VPPH1(min), between VPPH1 (max) and VPPH2(min) and above VPPH2(max). 4. Automatic Power Saving (APS) reduces ICCR to 1 mA typical in Static operation. 5. CMOS Inputs are either VCC 0.2V or GND 0.2V. TTL Inputs are either VIL or VIH. 6. Sampled, not 100% tested. Guaranteed by design.
36
E
tCE tOE tACC tAS tDH
28F016SV FlashFileTM MEMORY
5.5 Timing Nomenclature
All 3.3V system timings are measured from where signals cross 1.5V. For 5V systems use the standard JEDEC cross point definitions (standard testing) or from where signals cross 1.5V (high speed testing). Each timing parameter consists of 5 characters. Some common examples are defined below: tELQV time(t) from CE# (E) going low (L) to the outputs (Q) becoming valid (V) tGLQV time(t) from OE # (G) going low (L) to the outputs (Q) becoming valid (V) tAVQV time(t) from address (A) valid (V) to the outputs (Q) becoming valid (V) tAVWH time(t) from address (A) valid (V) to WE# (W) going high (H) tWHDX time(t) from WE# (W) going high (H) to when the data (D) can become undefined (X) Pin Characters A D Q E F G W P R V Y 5V 3V Address Inputs Data Inputs Data Outputs CE# (Chip Enable) BYTE# (Byte Enable) OE# (Output Enable) WE# (Write Enable) RP# (Deep Power-Down Pin) RY/BY# (Ready Busy) Any Voltage Level 3/5# Pin VCC at 4.5V Minimum VCC at 3.0V Minimum H L V X Z High Low Valid Driven, but Not Necessarily Valid High Impedance Pin States
37
28F016SV FlashFileTM MEMORY
5.6 AC Characteristics--Read Only Operations(1)
VCC = 3.3V 0.3V, T A = 0C to +70C, -40C to +85C Temp Sym Parameter Speed Notes tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH Read Cycle Time Address to Output Delay CE# to Output Delay RP# High to Output Delay OE# to Output Delay CE# to Output in Low Z CE# to Output in High Z OE# to Output in Low Z OE# to Output in High Z Output Hold from Address, CE# or OE# Change, Whichever Occurs First BYTE# to Output Delay BYTE# Low to Output in High Z CE# Low to BYTE# High or Low 2 3,8 3,8 3 3 3,8 0 0 20 0 0 30 0 20 0 2,8 Min 75 85(10) 75 85(10) 75 85(10) 480 40 0 50 0 Commercial -75 Max Extended -100 Min 100 100 100 620 45 0 Max
E
Commercial -120 Min 120 120 120 620 45 Max ns ns ns ns ns ns 50 ns ns 20 ns ns Units
tFLQV tFHQV tFLQZ tELFL tELFH
3 3 3,8
75 85(10) 30 5
100 30 5
120 30 5
ns ns ns
Extended Status Register Reads
tAVEL tAVGL Address Setup to CE# Going Low Address Setup to OE# Going Low 3,4, 8,9 3,4,9 0 0 0 0 0 0 ns ns
38
E
Sym tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH
28F016SV FlashFileTM MEMORY
5.6 AC Characteristics--Read Only Operations(1) (Continued)
VCC = 5V 0.5V, 5V 0.25V, TA = 0C to +70C, -40C to +85C Temp Speed Parameter VCC Load Notes Read Cycle Time Address to Output Delay CE# to Output Delay RP# to Output Delay OE# to Output Delay CE# to Output in Low Z CE# to Output in High Z OE# to Output in Low Z OE# to Output in High Z Output Hold from Address, CE# or OE# Change, Whichever Occurs First BYTE# to Output Delay 2 3,8 3,8 3 3 3,8 0 0 15 0 0 25 0 15 0 2,8 -65 5V 5%V 30 pF Min 65 65 65 400 30 0 25 0 20 Max Commercial -70 5V 10% 50 pF Min 70 70 70 480(6) 400(7) 30(6) 35(7) 0 30 35 ns ns ns ns ns ns Max Comm/Ext -80 5V 10% 50 pF Min 80 80 80 480 Max ns ns ns ns Units
tFLQV tFHQV tFLQZ tELFL tELFH
3
65
70
80
ns
BYTE# Low to Output in High Z CE# Low to BYTE# High or Low
3 3,8
25 5
25 5
30 5
ns ns
Extended Status Register Reads
tAVEL tAVGL Address Setup to CE# Going Low Address Setup to OE# Going Low 3,4,8,9 3,4,9 0 0 0 0 0 0 ns ns
39
28F016SV FlashFileTM MEMORY
NOTES: 1. See AC Input/Output Reference Waveforms for timing measurements, Figures 7 and 8. 2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE#, without impacting tELQV. 3. Sampled, not 100% tested. Guaranteed by design 4. This timing parameter is used to latch the correct BSR data onto the outputs. 5. Device speeds are defined as: 65/70 ns at VCC = 5V equivalent to 75 ns at VCC = 3.3V 70/80 ns at VCC = 5V equivalent to 120 ns at VCC = 3.3V 6. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit. 7. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit. 8. CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high. 9. The address setup requirement for Extended Status Register reads must only be met referenced to the falling edge of the last control signal to become active (CE0#, CE1# or OE#). For example, if CE0# and CE1# are activated prior to OE# for an Extended Status Register read, specification tAVGL must be met. On the other hand, if either CE0# or CE1# (or both) are activated after OE#, specification tAVEL must be referenced. 10. Page Buffer Reads only.
E
40
E
STANDBY V IH ADDRESSES (A) VIL t AVAV V IH V POWER-UP CC DEVICE AND ADDRESS SELECTION OUTPUTS ENABLED ADDRESSES STABLE CEx# (E) V IL
(1)
28F016SV FlashFileTM MEMORY
DATA VALID
STANDBY VCC POWER-DOWN
t AVEL t EHQZ
VIH OE# (G) V IL t AVGL t GHQZ
VIH WE# (W) V IL t ELQV t GLQX VOH DATA (D/Q) V OL HIGH Z VALID OUTPUT tELQX HIGH Z t GLQV t
OH
t AVQV
5.0V V CC GND t VIH RP# (P) V IL
0528_12
PHQV
NOTE: CEX # is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.
Figure 12. Read Timing Waveforms
41
28F016SV FlashFileTM MEMORY
E
ADDRESSES STABLE t AVAV
VIH ADDRESSES (A) V IL
V IH CEx #(E)
(1)
V IL
tAVFL = t ELFL
tEHQZ
V IH t AVEL OE# (G) V IL t ELFL t AVGL t FLQV = t AVQV t GHQZ
VIH BYTE# (F)
t GLQV V IL t ELQV t GLQX VOH DATA (DQ0-DQ7) VOL VOH DATA (DQ8-DQ15) VOL HIGH Z t AVQV HIGH Z t
OH
tELQX
DATA OUTPUT DATA OUTPUT ON DQ0-DQ7 HIGH Z
t FLQZ
DATA OUTPUT
HIGH Z
0528_13
NOTE: CEX # is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.
Figure 13. BYTE# Timing Waveforms
42
E
RP# (P)
28F016SV FlashFileTM MEMORY
5.7 Power-Up and Reset Timings
VCC POWER-UP
t YHPH
t YLPH
3/5#
(Y)
5.0V
t PLYL
3.3V
4.5V
VCC
0V
(3V,5V)
t PL5V
CE X #
t PHEL3
Address (A) Valid
t PHEL5
Valid
t AVQV
Data (Q)
Valid 3.3V Outputs
t AVQV
Valid 5.0V Outputs
t PHQV
t PHQV
0528_14
Figure 14. VCC Power-Up and RP# Reset Waveforms Symbol tPLYL tPLYH tYLPH tYHPH tPL5V tPL3V tPHEL3 tPHEL5 tAVQV tPHQV Parameter RP# Low to 3/5# Low (High) 3/5# Low (High) to RP# High RP# Low to VCC at 4.5V minimum (to VCC at 3.0V min or 3.6V max) RP# High to CE# Low (3.3V VCC) RP# High to CE# Low (5V VCC) Address Valid to Data Valid for VCC = 5V 10% RP# High to Data Valid for VCC = 5V 10% 1 2 1 1 3 3 Notes Min 0 2 0 405 330 70 400 Max Unit s s s ns ns ns ns
NOTES: CE0#, CE1# and OE# are switched low after Power-Up. 1. The tYLPH and/or tYHPH times must be strictly followed to guarantee all other read and program specifications for the 28F016SV. 2. The power supply may start to switch concurrently with RP# going low. 3. The address access time and RP# high to data valid time are shown for 5V VCC operation of the 28F016SV-070 (Standard Test Configuration). Refer to the AC Characteristics-Read Only Operations for 3.3V VCC and 5V VCC (High Speed Test Configuration) values.
43
28F016SV FlashFileTM MEMORY
5.8 AC Characteristics for WE#--Controlled Command Write Operations(1)
VCC = 3.3V 0.3V, T A = 0C to +70C; -40C to +85C
Temp Sym Parameter Speed Notes tAVAV tVPWH1,2 tPHEL tELWL tAVWH tDVWH tWLWH tWHDX tWHAX tWHEH tWHWL tGHWL tWHRL tRHPL Write Cycle Time VPP Setup to WE# Going High RP# Setup to CE# Going Low CE# Setup to WE# Going Low Address Setup to WE# Going High Data Setup to WE# Going High WE# Pulse Width Data Hold from WE# High Address Hold from WE# High CE# Hold from WE# High WE# Pulse Width High Read Recovery before Write WE# High to RY/BY# Going Low RP# Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High RP# High Recovery to WE# Going Low Write Recovery before Read VPP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High 3 3 3 3 0 2 2 3,7 3 3,7 3,7 2,6 2,6 Min 75 100 480 0,10(12) 60 60 60 5 5 5 15 0 100 0 Commercial -75 Typ Max Min 100 100 480 10 70 70 70 10 10 10 30 0 100 0 Extended -100 Typ Max Min 120 100 480 10 75 75 75 10 10 10 45 0 Commercial -120 Typ
E
Unit Max ns ns ns ns ns ns ns ns ns ns ns ns 100 ns ns
tPHWL tWHGL tQVVL1,2
3
0.480 55 0
1 75 0
1 95 0
s ns s
44
E
Sym tWHQV1 tWHQV2
28F016SV FlashFileTM MEMORY
5.8 AC Characteristics for WE#--Controlled Command Write Operations(1)
(Continued) VCC = 3.3V 0.3V, T A = 0C to +70C; -40C to +85C
Temp Parameter Speed Notes Duration of Program Operation Duration of Block Erase Operation 3,4,5, 11 3,4 Min 5 0.3 Commercial -75 Typ 9 0.8 Max TBD 10 Min 5 0.3 Extended -100 Typ 9 0.8 Max TBD 10 Min 5 0.3 Commercial -120 Typ 9 0.8 Max TBD 10 s sec Unit
45
28F016SV FlashFileTM MEMORY
5.8 AC Characteristics for WE#--Controlled Command Write Operations(1)
(Continued) VCC = 5V 0.5V, 5V 0.25V, TA = 0C to +70C, -40C to +85C Temp Speed Sym Parameter VCC Load Notes tAVAV Write Cycle Time 3 Min 65 100 -65 5V 5% 30 pF Typ Max Min 70 100 Commercial -70 5V 10% 50 pF Typ Max Min 80 100 Extended -80 5V 10% 50 pF Typ
E
Unit Max ns ns ns ns ns ns ns ns ns ns ns ns 100 ns
tVPWH1 VPP Setup to WE# Going High tVPWH2 tPHEL tELWL tAVWH tDVWH tWLWH tWHDX tWHAX tWHEH tWHWL tGHWL tWHRL RP# Setup to CE# Going Low CE# Setup to WE# Going Low Address Setup to WE# Going High Data Setup to WE# Going High WE# Pulse Width Data Hold from WE# High Address Hold from WE# High CE# Hold from WE# High WE# Pulse Width High Read Recovery before Write WE# High to RY/BY# Going Low RP# Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High
3,7 3,7 2,6 2,6
300 0 40 40 40
480(9) 300(10)
480 0 50 50 50 0 10 10 30 0 100
0 50(9) 40(10) 50(9) 40(10) 40(9) 45(10) 0 10 10(9) 5(10) 30(9) 15(10) 0 100
2 2 3,7
0 5 5 15
3 3
0
tRHPL
3
0
0
0
ns
46
E
Sym tPHWL tWHGL tQVVL1 tQVVL2
28F016SV FlashFileTM MEMORY
5.8 AC Characteristics for WE#--Controlled Command Write Operations(1)
(Continued) VCC = 5V 0.5V, 5V 0.25V, TA = 0C to +70C, -40C to +85C
Temp Speed Parameter VCC Load Notes RP# High Recovery to WE# Going Low Write Recovery before Read VPP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High 3,4,5, 11 3,4 4.5 0.3 6 0.6 TBD 10 4.5 0.3 6 0.6 TBD 10 4.5 0.3 6 0.6 TBD 10 s sec 3 3 Min 0.300 -65 5V 5% 30 pF Typ Max Min 1(9) 0.300(10) 55 0 60 0 65 0 ns s Commercial -70 5V 10% 50 pF Typ Max Min 1 Extended -80 5V 10% 50 pF Typ Max s Unit
tWHQV1 Duration of Program Operation tWHQV2 Duration of Block Erase Operation NOTES:
1. Read timings during program and erase are the same as for normal read. 2. Refer to command definition tables for valid address and data values. 3. Sampled, not 100% tested. Guaranteed by design. 4. Program/erase durations are measured to valid Status Register (CSR) Data. VPP = 12V 0.6V. 5. Word/byte program operations are typically performed with 1 Programming Pulse. 6. Address and Data are latched on the rising edge of WE# for all command write operations. 7. CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high. 8. Device speeds are defined as: 65/70 ns at VCC = 5V equivalent to 75 ns at VCC = 3.3V 70/80 ns at VCC = 5V equivalent to 120 ns at VCC = 3.3V 9. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit. 10. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit. 11. The TBD information will be available in a technical paper. Please contact Intel's Application Hotline or your local sales office for more information. 12. Page Buffer Programs only.
47
28F016SV FlashFileTM MEMORY
E
AUTOMATED DATA-WRITE OR ERASE DELAY WRITE READ EXTENDED REGISTER COMMAND READ EXTENDED STATUS REGISTER DATA A=RA t
WHAX
DEEP POWER-DOWN IH ADDRESSES (A) V NOTE 1 IL
V
WRITE DATA-WRITE OR ERASE SETUP COMMAND
WRITE VALID ADDRESS & DATA (DATA-WRITE) OR ERASE CONFIRM COMMAND A
IN
t
AVAV t
AVWH
NOTE 3
READ COMPATIBLE STATUS REGISTER DATA
IH ADDRESSES (A) V NOTE 2 IL t
AVAV
V
A t
IN
AVWH
t
WHAX
V
CEx # (E) NOTE 4 V
IH
IL
t
ELWL
t
WHEH
t
WHGL
V
OE# (G)
IH IL
V
t
WHWL
t
WHQV1,2
t
GHWL
V
WE# (W) V
IH
IL t t WLWH DVWH
D
t
WHDX
D
V
DATA (D/Q) V
IH
HIGH Z
t
IN
IN
D
IN
D
OUT
D
IN
IL
PHWL
t
WHRL
V RY/BY# (R) V
OH
OL
t V
RP# (P) V IH
RHPL
NOTE 5
IL
t
VPWH2
t
QVVL2
V V
V
PPH2
PP
(V) V
PPH1 t VPWH1 NOTE 6 t QVVL1
PPLK V IL NOTE 7
0528_15
NOTES: 1. This address string depicts data program/erase cycles with corresponding verification via ESRD. 2. This address string depicts data program/erase cycles with corresponding verification via CSRD. 3. This cycle is invalid when using CSRD for verification during data program/erase operations. 4. CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high. 5. RP# low transition is only to show tRHPL; not valid for above read and program cycles. 6. VPP voltage during program/erase operations valid at both 12V and 5V. 7. VPP voltage equal to or below VPPLK provides complete flash memory array protection.
Figure 15. AC Waveforms for Command Write Operations
48
E
Sym tAVAV tPHWL tWLEL tAVEH tDVEH tELEH tEHDX tEHAX tEHWH tEHEL tGHEL tEHRL tRHPL
28F016SV FlashFileTM MEMORY
5.9 AC Characteristics for CE#--Controlled Command Write Operations(1)
VCC = 3.3V 0.3V, T A = 0C +70C, -40C +85C Temp Parameter Speed Notes Write Cycle Time 3,7 3 3,7 2,6,7 2,6,7 7 2,7 2,7 3 7 3 3,7 3 0 Min 80 100 480 0 60 60 65 10 10 5 15 0 100 0 1 75 0 Commercial -80 Typ Max Min 100 100 480 0 70 70 70 10 30 0 100 Extended -100 Typ Max Min 120 100 480 0 75 75 75 10 10 10 45 0 100 Commercial -120 Typ Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
tVPEH1,2 VPP Setup to CE# Going High RP# Setup to WE# Going Low WE# Setup to CE# Going Low Address Setup to CE# Going High Data Setup to CE# Going High CE# Pulse Width Data Hold from CE# High Address Hold from CE# High WE# hold from CE# High CE# Pulse Width High Read Recovery before Write CE# High to RY/BY# Going Low RP# Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High RP# High Recovery to CE# Going Low Write Recovery before Read
tPHEL tEHGL
3,7
0.480 55
0
1 95
s ns
49
28F016SV FlashFileTM MEMORY
5.9 AC Characteristics for CE#--Controlled Command Write Operations(1)
(Continued) VCC = 3.3V 0.3V, T A = 0C +70C, -40C +85C Temp Sym Parameter Speed Notes tQVVL1,2 VPP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High tEHQV1 tEHQV2 3 Min 0 Commercial -80 Typ Max Min Extended -100 Typ Max Min 0
E
Unit s TBD 10 s sec
Commercial -120 Typ Max
Duration of Program 3,4,5,11 Operation Duration of Block Erase Operation 3,4
5 0.3
9 0.8
TBD 10
5 0.3
9 0.8
TBD 10
5 0.3
9 0.8
50
E
Sym tAVAV tPHWL tWLEL tAVEH tDVEH tELEH tEHDX tEHAX tEHWH tEHEL tGHEL tEHRL tRHPL
28F016SV FlashFileTM MEMORY
5.9 AC Characteristics for CE#--Controlled Command Write Operations(1)
(Continued) VCC = 5V 0.5V, 5V 0.25V, TA = 0 to +70C, -40C to +85C
Temp Speed Parameter VCC Load Notes Write Cycle Time 3,7 3 3,7 2,6,7 2,6,7 7 2,7 2,7 3,7 7 3 3,7 3 0 Min 65 100 300 0 40 40 45 0 10 5 15 0 100 0 -65 5V 5% 30 pF Typ Max Min 70 100 480(9) 300(10) 0 50(9) 45(10) 50(9) 45(10) 45(9) 50(10) 0 10 10(9) 5(10) 30(9) 15(10) 0 100 0 Commercial -70 5V 10% 50 pF Typ Max Min 80 100 480 0 50 50 50 0 10 10 30 0 100 Extended -80 5V 10% 50 pF Typ Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
tVPEH1,2 VPP Setup to CE# Going High RP# Setup to WE# Going Low WE# Setup to CE# Going Low Address Setup to CE# Going High Data Setup to CE# Going High CE# Pulse Width Data Hold from CE# High Address Hold from CE# High WE# Hold from CE# High CE# Pulse Width High Read Recovery before Write CE# High to RY/BY# Going Low RP# Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High
51
28F016SV FlashFileTM MEMORY
5.9 AC Characteristics for CE#--Controlled Command Write Operations(1)
(Continued) VCC = 5V 0.5V, 5V 0.25V, TA = 0 to +70C, -40C to +85C
Temp Speed Sym Parameter VCC Load Notes tPHEL tEHGL RP# High Recovery to CE# Going Low Write Recovery before Read 3 3,7 Min 0.300 55 0 -65 5V 5% 30 pF Typ Max Min 1(9) 0.300(10) 60 0 Commercial -70 5V 10% 50 pF Typ Max Min 1 65 0
E
Unit Max s ns s
Extended -80 5V 10% 50 pF Typ
tQVVL1,2 VPP Hold from Valid Status Register (CSR, GSR, BSR) Data at RY/BY# High tEHQV1 tEHQV2 Duration of Program Operation Duration of Block Erase Operation
3,4,5,11 3,4
4.5 0.3
6 0.6
TBD 10
4.5 0.3
6 0.6
TBD 10
4.5 0.3
6 0.6
TBD 10
s sec
NOTES: 1. Read timings during program and erase are the same as for normal read. 2. Refer to command definition tables for valid address and data values. 3. Sampled, not 100% tested. Guaranteed by design. 4. Program/erase durations are measured to valid Status Data. VPP = 12V 0.6V. 5. Word/byte program operations are typically performed with 1 Programming Pulse. 6. Address and Data are latched on the rising edge of CE# for all command write operations. 7. CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high. 8. Device speeds are defined as: 65/70 ns at VCC = 5V equivalent to 75 ns at VCC = 3.3V 70/80 ns at VCC = 5V equivalent to 120 ns at VCC = 3.3V 9. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit. 10. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit. 11. The TBD information will be available in a technical paper. Please contact Intel's Application Hotline or your local sales office for more information.
52
E
DEEP POWER-DOWN IH ADDRESSES (A) V NOTE 1 IL t
AVAV t V
28F016SV FlashFileTM MEMORY
WRITE DATA-WRITE OR ERASE SETUP COMMAND
WRITE VALID ADDRESS & DATA (DATA-WRITE) OR ERASE CONFIRM COMMAND A
AUTOMATED DATA-WRITE OR ERASE DELAY
WRITE READ EXTENDED REGISTER COMMAND
READ EXTENDED STATUS REGISTER DATA
IN
A=RA t
EHAX
AVEH
NOTE 3
READ COMPATIBLE STATUS REGISTER DATA
IH ADDRESSES (A) V IL NOTE 2 t
AVAV
V
A t
IN
AVEH
t
EHAX
V
WE# (W) V
IH
IL
t
WLEL
t
EHWH
t
EHGL
V
OE# (G)
IH IL
V
t
EHEL
t
EHQV1,2
t
GHEL
V CEx#(E)
V
IH
NOTE 4
IL t t ELEH DVEH
D
t
EHDX
D
V
DATA (D/Q) V
IH
HIGH Z
t
IN
IN
D
IN
D
OUT
D
IN
IL
PHEL
t
EHRL
V RY/BY# (R) V
OH
OL
t V
RP# (P) V IH
RHPL
NOTE 5
IL
t
VPEH2
t
QVVL2
V V
(V) V PP V V
PPH2
PPH1 PPLK IL NOTE 7 t
NOTE 6 VPEH1 t
QVVL1
0528_16
NOTES: 1. This address string depicts data program/erase cycles with corresponding verification via ESRD. 2. This address string depicts data program/erase cycles with corresponding verification via CSRD. 3. This cycle is invalid when using CSRD for verification during data program/erase operations. 4. CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high. 5. RP# low transition is only to show tRHPL; not valid for above read and write cycles. 6. VPP voltage during program/erase operations valid at both 12V and 5V. 7. VPP voltage equal to or below VPPLK provides complete flash memory array protection.
Figure 16. Alternate AC Waveforms for Command Write Operations
53
28F016SV FlashFileTM MEMORY
5.10 AC Characteristics for WE#--Controlled Page Buffer Write Operations(1)
VCC = 3.3V 0.3V, T A = 0C to +70C, -40C to +85C Temp Sym Parameter Speed Notes tAVWL Address Setup to WE# Going Low 2 Min 0 Commercial/Extended -75, -100, -120 Typ Max
E
Unit ns Unit
VCC = 5V 0.5V, 5V 0.25V, TA = 0C to +70C, -40C to +85C Temp Speed Sym Parameter VCC Load Notes tAVWL Address Setup to WE# Going Low 2 Min 0 -65 5V 5% 30 pF Typ Max Min 0 Commercial -70 5V 10% 50 pF Typ Max Min 0 Comm/Ext -80 5V 10% 50 pF Typ Max ns
NOTES: 1. All other specifications for WE#--Controlled Write Operations can be found in section 5.8. 2. Address must be valid during the entire WE# low pulse. 3. Device speeds are defined as: 65/70 ns at VCC = 5V equivalent to 75 ns at VCC = 3.3V 70/80 ns at VCC = 5V equivalent to 120 ns at VCC = 3.3V 4. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit. 5. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.
54
E
V CEx# (E) Note 1
IH
28F016SV FlashFileTM MEMORY
V
IL
t WHEH t ELWL V WE# (W)
IH
t WHWL V
IL
t AVWL t WLWH t
WHAX
V
IH
ADDRESSES (A) V
IL
VALID
t DVWH V DATA (D/Q) V
IH
t WHDX
HIGH Z DIN
IL
0528_17
NOTE: 1. CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.
Figure 17. WE#--Controlled Page Buffer Write Timing Waveforms (Loading Data to the Page Buffer)
55
28F016SV FlashFileTM MEMORY
5.11 AC Characteristics for CE#--Controlled Page Buffer Write Operations(1)
VCC = 3.3V 0.3V, T A = 0C to +70C, -40C to +85C Temp Sym Parameter Speed Notes tAVEL Address Setup to CE# Going Low 2,3 Min 0 Commercial/Extended -75, -100, -120 Typ Max
E
Unit ns Unit
VCC = 5V 0.5V, 5V 0.25V, TA = 0C to +70C, -40C to +85C Temp Speed Sym Parameter VCC Load Notes tAVEL Address Setup to CE# Going Low 2,3 Min 0 -65 5V 5% 30 pF Typ Max Min 0 Commercial -70 5V 10% 50 pF Typ Max Min 0 Comm/Ext -80 5V 10% 50 pF Typ Max ns
NOTES: 1. All other specifications for CE#--Controlled Write Operations can be found in Section 5.9. 2. Address must be valid during the entire WE# low pulse. 3. CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high. 4. Device speeds are defined as: 65/70 ns at VCC = 5V equivalent to 75 ns at VCC = 3.3V 70/80 ns at VCC = 5V equivalent to 120 ns at VCC = 3.3V 5. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit. 6. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.
56
E
V WE# (W)
IH
28F016SV FlashFileTM MEMORY
V
IL
t EHWH t WLEL V CEx# (E) Note 1
IH
t EHEL V
IL
t AVEL t ELEH t
EHAX
V
IH
ADDRESSES (A) V
IL
VALID
t DVEH V DATA (D/Q) V
IH
t EHDX
HIGH Z DIN
IL
0528_18
NOTE: 1. CEx# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.
Figure 18. CE#--Controlled Page Buffer Write Timing Waveforms (Loading Data to the Page Buffer)
57
28F016SV FlashFileTM MEMORY
5.12 Erase and Word/Byte Program Performance(3,5)
VCC = 3.3V 0.3V, V PP = 5V 0.5V, TA = 0C to +70C Symbol Parameter Page Buffer Byte Write Time Page Buffer Word Write Time tWHRH1A tWHRH1B tWHRH2 tWHRH3 Byte Program Time Word Program Time Block Program Time Block Program Time Block Erase Time Full Chip Erase Time Erase Suspend Latency Time to Read Auto Erase Suspend Latency Time to Program Notes 2,6,7 2,6,7 2,7 2,7 2,7 2,7 2,7 2,7 4 Min TBD TBD TBD TBD TBD TBD TBD TBD 1.0 4.0 Typ(1) 8.0 16.0 29.0 35.0 1.9 1.2 1.4 44.8 12 15 Max TBD TBD TBD TBD TBD TBD TBD TBD 75 80 Units s s s s sec sec sec sec s s
E
Test Conditions Byte Prog. Mode Word Prog. Mode
VCC = 3.3V 0.3V, V PP = 12V 0.6V, T A = 0C to +70C Symbol Parameter Page Buffer Byte Write Time Page Buffer Word Write Time tWHRH1 tWHRH2 tWHRH3 Word/Byte Program Time Block Program Time Block Program Time Block Erase Time Full Chip Erase Time Erase Suspend Latency Time to Read Auto Erase Suspend Latency Time to Program Notes 2,6,7 2,6,7 2,7 2,7 2,7 2 2,7 4 Min TBD TBD 5 TBD TBD 0.3 TBD 1.0 4.0 Typ(1) 2.2 4.4 9 0.6 0.3 0.8 25.6 9 12 Max TBD TBD TBD 2.1 1.0 10 TBD 55 60 Units s s s sec sec sec sec s s Byte Prog. Mode Word Prog. Mode Test Conditions
58
E
Symbol tWHRH1A tWHRH1B tWHRH2 tWHRH3
28F016SV FlashFileTM MEMORY
5.12 Erase and Word/Byte Program Performance(3,5) (Continued)
VCC = 5V 0.5V, 5V 0.25V, V PP = 5V 0.5V, T A = 0C to +70C Parameter Page Buffer Byte Write Time Page Buffer Word Write Time Byte Program Time Word Program Time Block Program Time Block Program Time Block Erase Time Full Chip Erase Time Erase Suspend Latency Time to Read Auto Erase Suspend Latency Time to Program Notes 2,6,7 2,6,7 2,7 2,7 2,7 2,7 2,7 2,7 4 Min TBD TBD TBD TBD TBD TBD TBD TBD 1.0 3.0 Typ(1) 8.0 16.0 20 25 1.4 0.85 1.0 32.0 9 12 Max TBD TBD TBD TBD TBD TBD TBD TBD 55 60 Units s s s s sec sec sec sec s s Byte Prog. Mode Word Prog. Mode Test Conditions
VCC = 5V 0.5V, 5V 0.25V, V PP = 12V 0.6V, T A = 0C to +70C Symbol Parameter Page Buffer Byte Write Time Page Buffer Word Write Time tWHRH1 tWHRH2 tWHRH3 Word/Byte Program Time Block Program Time Block Program Time Block Erase Time Full Chip Erase Time Erase Suspend Latency Time to Read Auto Erase Suspend Latency Time to Program Notes 2,6,7 2,6,7 2,7 2,7 2,7 2 2,7 4 Min TBD TBD 4.5 TBD TBD 0.3 TBD 1.0 3.0 Typ(1) 2.1 4.1 6 0.4 0.2 0.6 19.2 7 10 Max TBD TBD TBD 2.1 1.0 10 TBD 40 45 Units s s s sec sec sec sec s s Byte Prog. Mode Word Prog. Mode Test Conditions
NOTES: 1. +25C, and nominal voltages. 2. Excludes system-level overhead. 3. These performance numbers are valid for all speed versions. 4. Specification applies to interrupt latency for single block erase. Suspend latency for erase all unlocked blocks operation extends the maximum latency time to 270 s. 5. Sampled, but not 100% tested. Guaranteed by design. 6. Assumes using the full Page Buffer to Program to Flash (256 bytes or 128 words). 7. The TBD information will be available in a technical paper. Please contact Intel's Application Hotline or your local sales office for more information.
59
28F016SV FlashFileTM MEMORY
6.0 MECHANICAL SPECIFICATIONS
E
048928.eps
Figure 19. Mechanical Specifications of the 28F016SV 56-Lead TSOP Type I Package Family: Thin Small Out-Line Package Symbol Minimum A A1 A2 b c D1 E e D L N Y Z 0.150 0.250 0 19.80 0.500 0.050 0.965 0.100 0.115 18.20 13.80 0.995 0.150 0.125 18.40 14.00 0.50 20.00 0.600 56 3 5 0.100 0.350 20.20 0.700 1.025 0.200 0.135 18.60 14.20 Millimeters Nominal Maximum 1.20 Notes
60
E
E He A2 D A B e 1 Y C A1
28F016SV FlashFileTM MEMORY
a R1
b R2 L1 Detail A
See Detail A
0528_20
Figure 20. Mechanical Specifications of the 28F016SV 56-Lead SSOP Type I Package Family: Shrink Small Out-Line Package Symbol Minimum A A1 A2 B C D E e1 He N L1 Y a b R1 R2 2 3 0.15 0.15 3 4 0.20 0.20 0.45 15.70 0.47 1.18 0.25 0.13 23.40 13.10 Millimeters Nominal 1.80 0.52 1.28 0.30 0.15 23.70 13.30 0.80 16.00 56 0.50 0.55 0.10 4 5 0.25 0.25 16.30 Maximum 1.90 0.57 1.38 0.40 0.20 24.00 13.50 Notes
61
28F016SV FlashFileTM MEMORY
APPENDIX A DEVICE NOMENCLATURE AND ORDERING INFORMATION
Product line designator for all Intel Flash products
E
E 2 8 F 0 1 6 SV - 0 6 5
Package DA = Commercial Temp. 56-Lead SSOP E = Commercial Temp. 56-Lead TSOP T = Extended Temp. 56-Lead SSOP Device Density 016 = 16 Mbit
Access Speed (ns) 65 ns (5V, 30 pF), 70 ns (5V), 75 ns (3.3V) 70 ns (5V, 30 pF), 80 ns (5V), 120 ns (3.3V)
Device Type V = SmartVoltage Product Family S = FlashFileTM Memory
0528_21
Valid Combinations Option Order Code VCC = 3.3V 0.3V, 50 pF load, 1.5V I/O Levels(1) E28F016SV-120 E28F016SV-075 DA28F016SV-120 DA28F016SV-075 DT28F016SV-100 VCC = 5V 10%, 100 pF load TTL I/O Levels(1) E28F016SV-080 E28F016SV-070 DA28F016SV-080 DA28F016SV-070 DT28F016SV-080 VCC = 5V 5%, 30 pF load 1.5V I/O Levels(1) E28F016SV-070 E28F016SV-065 DA28F016SV-070 DA28F016SV-065 DT28F016SV-080
1 2 3 4 5
E28F016SV 070 E28F016SV 065 DA28F016SV 070 DA28F016SV 065 DT28F016SV 080
NOTE: 1. See Section 5.2 for Transient Input/Output Reference Waveforms and Testing Load Circuits.
62
E
Order Number 297372 290429 290490 292092 292123 292126 292144 292159 292163 292165 294016 297508
28F016SV FlashFileTM MEMORY
APPENDIX B ADDITIONAL INFORMATION(1,2)
Document/Tool
16-Mbit Flash Product Family User's Manual 28F008SA Datasheet DD28F032SA 32-Mbit (2 bit x 16, 4 Mbit x 8) FlashFileTM Memory Datasheet) AP-357 Power Supply Solutions for Flash Memory AP-374 Flash Memory Write Protection Techniques AP-377 16-Mbit Flash Product Family Software Drivers, 28F016SA/28F016SV/28F016XS/28F016XD AP-393 28F016SV Compatibility with 28F016SA AP-607 Multi-Site Layout Planning with Intel's FlashFileTM Components, Including ROM Capability AP-610 Flash Memory In-System Code and Data Update Techniques AB-62 Compiled Code Optimizations for Flash Memories ER-33 ETOXTM Flash Memory Technology--Insight to Intel's Fourth Generation Process Innovation
FLASHBuilder Utility Flash Cycling Utility 28F016SV iBIS Model 28F016SV VHDL 28F016SV Timing Designer Library Files 28F016SV Orcad and ViewLogic Schematic Symbols
Contact Intel/Distribution Sales Office Contact Intel/Distribution Sales Office Contact Intel/Distribution Sales Office Contact Intel/Distribution Sales Office Contact Intel/Distribution Sales Office
NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel's World Wide Web home page at http://www.Intel.com for technical documentation and tools.
63

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